Why is it important to understand the instruction cycle

A FIFO is a First In First Out i> store. You can imagine that data is shifted at one end and shifted out at the other, whereby the amount of data in the FIFO is allowed to grow up to a maximum limit.

However, moving data in memory is actually expensive to do in hardware. A better option is to use a memory more normally, but make it look like a ring buffer by manipulating the next address to write to and read from. These addresses are in separate registers and are often referred to as Read pointer i> and Writing pointer i> denotes.

Here is a representation of the state for a simple FIFO with an 8-word memory:

The next incoming word is written to the empty word at address 1 (the value of the write pointer), then incremented to 2 in the write pointer. On the next read request, the word is fetched at 5 (the value of the read pointer), then the read pointer is incremented by 1. In this example, the addresses are automatically circular if the pointers are 3 bits wide. Adding 1 to 7 results in 0 in unsigned 3-bit math.

Complete FIFO systems need ways to identify the complete and empty conditions. There are different schemes for this. A separate register could be used to keep track of how many words are in the FIFO, which is in snapshot 4 shown above.

A useful scheme for a firmware implementation is to compare the read and write pointers. For example, you can decide that both pointers are equally FIFO empty and one after read (after the break) FIFO is full. Note that one word of the FIFO is not used in such schemes. In the end, you output a piece of state somewhere to see if it is a separate register or a useless word in the FIFO. The advantage of this scheme is that read and write operations can take place independently of one another without conflicts, so that such a FIFO does not require a mutex between read and write. For example, you do not need to disable interrupts while reading, as there is no damage if an interrupt routine pushes a word onto the FIFO while the foreground code is trying to read.