What is the leakage current in CMOS

Check leakage currents in SoCs

A consortium with 14 partners from universities, industry and research in 7 European countries starts "CLEAN" - a project that develops innovative design methods to control leakage currents in CMOS designs below 65nm.

The CLEAN project (Controlling Leakage power in Na-noCMOS SoCs) is funded by the European Union with 4.5 million euros from the nanoelectronics focus of the sixth research framework program (IST FP6). The aim of the project is to improve the design of the next SoC (System on Chip) generation by taking care of the key effect of leakage currents in CMOS technologies in 65nm and below.

In microelectronic circuits with structure sizes over 0.1 micrometers, the dynamic power loss - which occurs during the calculation, transmission and storage of data - dominates over the leakage currents of the transistors.

The importance of leakage currents has grown enormously with the advent of nanoelectronic components with structure sizes below 100 nm. Leakage currents will be the biggest hurdle in systems below 65nm. In order to cope with the difficulties that arise with nanoelectronic systems, design and process development must work hand in hand. Future semiconductor design will have to take into account the complexity, cost, and power requirements of the systems that are being designed, manufactured, and tested.

The main goals of CLEAN are the development of new forecast models, design methods and techniques to control leakage currents as prototypical EDA (Electronic Design Automation) tools, which do the parts of the design work that are still unthinkable for complex systems today - for example design tasks for energy reduction and for the end-to-end implementation of leakage current control techniques. The CLEAN project is led by STMicroelectronics and coordinated together with the IT institute OFFIS, Oldenburg.

"The project will make a significant contribution to overcoming the technological disadvantages below 65nm, in particular the process fluctuations, the reliability and the leakage currents", says the project coordinator Roberto Zafalon, R&D program manager, Advanced System Technology at the project manager STMicroelectronics. "The results of the CLEAN project will simultaneously enable a reduction in the power loss of nanoelectronic systems and an increase in design productivity, in order to make the increased SoC complexity manageable."

In addition, the CLEAN project helps to strengthen Europe's high-tech industry in the areas in which it already has industrial and technological leadership - for example SoC for mobile communication and infrastructure, consumer electronics and automotive electronics. In these areas, a low energy requirement is a prerequisite for success!

Thanks to the participation of small and medium-sized high-tech companies such as ChipVision Design Systems and BullDAST, which have specialized in tools for energy reduction, the project also promotes the development of the European EDA industry. Their role will be the key to exploiting the CLEAN results in commercial and industrial applications.

The partners in the CLEAN project are:
STMicroelectronics (project manager); Locations in Italy and France
ChipVision Design Systems
Politecnico di Torino
Universitat Politecnica de Catalunya
Politechnika Warszawska
Technical University of Denmark
Consorzio per la Ricerca e l’Educazione Permanente
Budapest University of Technology and Economics

Contact person for queries from the editorial team:
Dr. Jens Appell, OFFIS Head of Department "Embedded Hardware / Software Systems"
Tel. (04 41) 97 22-235, fax (04 41) 97 22 - 102, email: appellatoffis.de

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